The minimum voltage at which an integrated circuit (IC) can reliably operate is referred to as the IC's VCC_min. As the proliferation of mobile devices have driven up the demand for scaled-down ICs and processors that consume less power, the VCC_min of most ICs have continued to decrease. However, this trend of ever decreasing VCC_min has taken a toll on the reliability of certain IC components. For example, ICs often embed and employ a static random access memory (SRAM) circuit to handle on-chip storage needs. The SRAM cell is often arranged as an array comprising rows and columns. In a conventional SRAM cell, each row of the cell is coupled to a word line and each column is coupled to a pair of bit-lines. As the VCC_min of SRAM circuits decrease, the read and write operation margins of the underlying SRAM cell also decrease due to voltage noise.
Various solutions to this problem have been proposed to maintain the reliability of write operations at reduced VCC_min. These include: VDD lowering, VSS raising, word-line boosting, and negative bit-line manipulations. However, all such solutions are geared toward traditional six transistor (6T) SRAM cells and require peripheral circuitry that may further complicate memory design, consume more dynamic power, and affect unselected cells in the same row. Moreover, solutions that embed write assist into the SRAM cell structure have faced significant DC current problems that have an adverse impact on unselected cells. Therefore, a design solution is needed that addresses the above mentioned problems.